Methods For Forming A Transparent Oxide Layer For A Photovoltaic Device

ABSTRACT

A method of manufacturing a transparent oxide layer is provided. The manufacturing method includes disposing a cadmium tin oxide layer on a support, placing the support with the cadmium tin oxide layer within a chamber of a rapid thermal annealing system, and rapidly thermally annealing the cadmium tin oxide layer by exposing the cadmium tin oxide layer to electromagnetic radiation to form the transparent oxide layer, wherein the rapid thermal anneal is performed without first pumping down the chamber.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation in part of U.S. patent applicationSer. No. 12/972,242, Joseph Darryl Michael et al., entitled “Method forforming cadmium tin oxide layer and a photovoltaic device,” which patentapplication is hereby incorporated by reference herein in its entirety.

BACKGROUND

The invention relates to methods for forming photovoltaic (PV) devices.More particularly, the invention relates to methods for forming atransparent oxide layer in a photovoltaic device.

PV (or solar) cells are used for converting solar energy into electricalenergy. Typically, in its basic form, thin film solar cells orphotovoltaic devices typically include a number of semiconductor layersdisposed on a transparent support, where one semiconductor layer servesas a window layer, and a second semiconductor layer serves as anabsorber layer. Solar radiation travels through the window layer to theabsorber layer, where the optical energy is converted to usableelectrical energy. Additional layers are often employed to enhance theconversion efficiency of the PV device.

There are a variety of candidate material systems for PV cells, each ofwhich has certain advantages and disadvantages. Cadmiumtelluride/cadmium sulfide (CdTe/CdS) heterojunction-based photovoltaiccells are one such example of thin film solar cells.

Typically, a thin layer of transparent conductive oxide (TCO) isdeposited between the support and the window layer (for example, CdS) tofunction as a front contact current collector. However conventionalTCOs, such as fluorine-doped tin oxide, indium tin oxide, andaluminum-doped zinc oxide, have high electrical resistivities at thethicknesses necessary for good optical transmission. The use of cadmiumtin oxide (CTO) as a TCO provides better electrical, optical, andmechanical properties, as well as stability at elevated temperatures. Inaddition, for certain configurations, to achieve high deviceefficiencies with thin CdS films, a thin layer of a buffer material,such as an undoped tin oxide (SnO₂) layer, may be intercalated betweenthe cadmium tin oxide (CTO) and the window (CdS) layers.

Typically, to form a transparent CTO layer, a layer of amorphous cadmiumtin oxide is deposited on a support, followed by slow thermal annealingof the CTO layer, which is in contact or in close proximity with a CdSfilm, to achieve desired transparency and resistivity. However,CdS-based annealing of CTO is difficult to implement in a large-scalemanufacturing environment. Specifically, it is very difficult toassemble and disassemble the plates before and after the annealingprocess, typically requiring manual intervention of the operator, andthere is a high risk of misalignment that may result in the sublimationof the CTO film. Further, the use of expensive CdS on a non-reusableglass plate for each annealing step increases the cost of manufacturing.The high annealing temperatures (>550° C.) employed for thermalprocessing of the CTO film, further do not allow for the use of lessexpensive low softening temperature supports, such as, for example,soda-lime glass.

After crystallization of CTO is achieved, a separate buffer layer (forexample, undoped tin oxide) may be deposited on the CTO layer, which maybe further followed by a second annealing step to obtain goodcrystalline quality. The performance of the buffer layer usually dependsin part on the crystallinity and morphology of that layer and isaffected by the surface of the CTO on which it is deposited. A highquality buffer layer is desirable to obtain the desired performance inthe solar cells manufactured therefrom.

Thus, there is a need to reduce the number of steps for depositing andannealing of CTO and optional buffer layers during manufacturing ofphotovoltaic devices, resulting in reduced costs and improvedmanufacturing capability. Further, there is a need to providecost-effective electrodes and photovoltaic devices manufactured usingcadmium tin oxide having the desired electrical and optical properties.

BRIEF DESCRIPTION

One aspect of the present invention resides in a method of manufacturinga transparent oxide layer. The manufacturing method includes disposing acadmium tin oxide layer on a support, placing the support with thecadmium tin oxide layer within a chamber of a rapid thermal annealingsystem, and rapidly thermally annealing the cadmium tin oxide layer byexposing the cadmium tin oxide layer to electromagnetic radiation toform the transparent oxide layer. The rapid thermal anneal is performedwithout first pumping down the chamber.

Another aspect of the present invention resides in a method ofmanufacturing a transparent oxide layer. The manufacturing methodincludes disposing a cadmium tin oxide layer on a support, placing thesupport with the cadmium tin oxide layer within a chamber of a rapidthermal annealing system, and rapidly thermally annealing the cadmiumtin oxide layer by exposing the cadmium tin oxide layer toelectromagnetic radiation to form the transparent oxide layer. Air isdisposed within the chamber during the rapid thermal anneal at aconcentration of at least one percent (1%) by volume.

DRAWINGS

These and other features, aspects, and advantages of the presentinvention will become better understood when the following detaileddescription is read with reference to the accompanying drawings in whichlike characters represent like parts throughout the drawings, wherein:

FIG. 1 schematically depicts, in cross-sectional view, a cadmium tinoxide layer disposed on a support, for use as a transparent oxide layerin a photovoltaic device;

FIG. 2 schematically depicts, in cross-sectional view, a barrier layerdisposed between the cadmium tin oxide layer and the support shown inFIG. 1;

FIG. 3 schematically depicts, in cross-sectional view, a resistive,transparent buffer layer disposed on the cadmium tin oxide layer/supportassembly shown in FIG. 1;

FIG. 4 schematically depicts, in cross-sectional view, a conductivelayer disposed on the cadmium tin oxide layer/support assembly shown inFIG. 1;

FIG. 5 schematically depicts, in cross-sectional view, a conductivelayer disposed on the cadmium tin oxide layer/barrier layer/supportassembly shown in FIG. 2;

FIG. 6 schematically depicts, in cross-sectional view, a resistive,transparent buffer layer disposed on the conductive layer/cadmium tinoxide layer/barrier layer/support assembly shown in FIG. 5;

FIG. 7 schematically depicts, in cross-sectional view, a semiconductorlayer disposed on the resistive, transparent buffer layer/conductivelayer/cadmium tin oxide layer/barrier layer/support assembly shown inFIG. 6;

FIG. 8 schematically depicts, in cross-sectional view, a photovoltaicdevice that includes a transparent oxide layer formed using themanufacturing method of the present invention; and

FIG. 9 schematically depicts a cadmium tin oxide layer/support assemblydisposed within a chamber of a rapid thermal annealing system forin-line rapid thermal annealing of the cadmium tin oxide layer.

DETAILED DESCRIPTION

The terms “first,” “second,” and the like, herein do not denote anyorder, quantity, or importance, but rather are used to distinguish oneelement from another. The terms “a” and “an” herein do not denote alimitation of quantity, but rather denote the presence of at least oneof the referenced items. The modifier “about” used in connection with aquantity is inclusive of the stated value, and has the meaning dictatedby context, (e.g., includes the degree of error associated withmeasurement of the particular quantity). In addition, the term“combination” is inclusive of blends, mixtures, alloys, reactionproducts, and the like.

Moreover, in this specification, the suffix “(s)” is usually intended toinclude both the singular and the plural of the term that it modifies,thereby including one or more of that term. Reference throughout thespecification to “one embodiment,” or “another embodiment,” “anembodiment,” and so forth, means that a particular element (e.g.,feature, structure, and/or characteristic) described in connection withthe embodiment is included in at least one embodiment described herein,and may or may not be present in other embodiments. Similarly, referenceto “a particular configuration” means that a particular element (e.g.,feature, structure, and/or characteristic) described in connection withthe configuration is included in at least one configuration describedherein, and may or may not be present in other configurations. Inaddition, it is to be understood that the described inventive featuresmay be combined in any suitable manner in the various embodiments andconfigurations.

In addition, approximating language, as used herein throughout thespecification and claims, may be applied to modify any quantitativerepresentation that could permissibly vary without resulting in a changein the basic function to which it is related. Accordingly, a valuemodified by a term or terms, such as “about”, is not limited to theprecise value specified. In some instances, the approximating languagemay correspond to the precision of an instrument for measuring thevalue.

Further, the terms “transparent region”, “transparent layer” and“transparent electrode” as used herein, refer to a region, a layer, oran article that allows an average transmission of at least 80% ofincident electromagnetic radiation having a wavelength in a range fromabout 300 nm to about 850 nm. As used herein, the term “disposed on”refers to layers disposed directly in contact with each other orindirectly by having intervening layers there between.

A method of manufacturing a transparent oxide layer 120 is describedwith reference to FIGS. 1-9. As indicated in FIG. 1, the manufacturingmethod includes disposing a cadmium tin oxide (CTO) layer 120 on asupport 110. The CTO layer 120 may be disposed directly on the support,as indicated in FIG. 1, or one or more intervening layers may bedisposed between the CTO layer 120 and the support 110, as discussedbelow with reference to FIG. 2.

As used herein, the term “cadmium tin oxide” refers to a composition ofcadmium, tin, and oxygen. For certain configurations, the cadmium tinoxide may comprise a stoichiometric composition of cadmium and tin,where, for example, the atomic ratio of cadmium to tin is about 2:1. Forother configurations, the cadmium tin oxide may comprise anon-stoichiometric composition of cadmium and tin, where, for example,the atomic ratio of cadmium to tin is in range less than about 2:1 orgreater than about 2:1. As used herein, the terms “cadmium tin oxide”and “CTO” may be used interchangeably. The cadmium tin oxide may furtherinclude one or more dopants, such as, for example, copper, zinc,calcium, yttrium, zirconium, hafnium, vanadium, tin, ruthenium,magnesium, indium, zinc, palladium, rhodium, titanium, or combinationsthereof. “Substantially amorphous cadmium tin oxide” as used hereinrefers to a cadmium tin oxide layer that does not have a distinctcrystalline pattern as observed by X-ray diffraction (XRD). The CTOlayer 120 will typically be deposited as a substantially amorphous CTOlayer, as discussed below.

The cadmium tin oxide may function as a transparent conductive oxide(TCO). The use of cadmium tin oxide as a TCO has numerous advantagesincluding superior electrical, optical, surface, and mechanicalproperties and increased stability at elevated temperatures whencompared to tin oxide, indium oxide, indium tin oxide, and othertransparent conductive oxides. The electrical properties of cadmium tinoxide may depend in part on the composition of cadmium tin oxidecharacterized in some embodiments by the atomic concentration of cadmiumand tin, or alternatively in some other embodiments by the atomic ratioof cadmium to tin in cadmium tin oxide. The atomic ratio of cadmium totin, as used herein, refers to the ratio of the atomic concentration ofcadmium to tin in cadmium tin oxide. Atomic concentrations of cadmiumand tin and the corresponding atomic ratio are commonly measured using,for instance, x-ray photoelectron spectroscopy (XPS).

For particular configurations, the atomic ratio of cadmium to tin in theCTO layer 120 is in a range from about 1.2:1 to about 3:1, and moreparticularly, in a range from about 1.5:1 to about 2.5:1, and still moreparticularly, in a range from about 1.7:1 to about 2.15:1. Forparticular configurations, the atomic ratio of cadmium to tin in the CTOlayer 120 is in a range from about 1.4:1 to about 2:1.

For particular configurations, the atomic concentration of cadmium inthe CTO layer 120 may be in a range of about 20-40% of the total atomiccontent of the CTO, and more particularly, in a range of about 25-35% ofthe total atomic content of the CTO, and still more particularly, about28-32% of the total atomic content of the CTO. For particularconfigurations, the atomic concentration of tin in the CTO layer 120 maybe in a range of about 10-30% of the total atomic content of the CTO,and more particularly, in a range of about 15-28% of the total atomiccontent of the CTO, and still more particularly, in a range of about18-24% of the total atomic content of the CTO. For particularconfigurations, the atomic concentration of oxygen in the CTO layer 120may be in a range of about 30-70% of the total atomic content of theCTO, and more particularly, in a range of about 40-60% of the totalatomic content of the CTO, and still more particularly, in a range ofabout 44-50% of the total atomic content of the CTO.

The CTO layer 120 may be disposed on the support 110 by any suitabletechnique, such as sputtering, chemical vapor deposition, spin coating,spray coating, or dip coating. For example, a substantially amorphousCTO layer 120 may be formed by dipping a support 110 into a solution ofa reaction product containing cadmium and tin derived from a cadmiumcompound and a tin compound.

A substantially amorphous CTO layer 120 may also be disposed on thesupport 110 by sputtering. For example, the CTO layer 120 may bedisposed on the support 110 by radio frequency (RF) sputtering or directcurrent (DC) sputtering. The CTO layer 120 may also be disposed on thesupport 110 by reactive sputtering in the presence of oxygen.

For particular processes, a ceramic cadmium tin oxide target may be usedin disposing a substantially amorphous CTO layer 120 on the support 110.For other processes, a substantially amorphous CTO layer 120 may bedisposed on the support 110 by co-sputtering using cadmium oxide and tinoxide targets or by sputtering from a single target including a blend ofcadmium oxide and tin oxide. Reactive sputtering may also be employedusing a single metallic target, where the metal target includes amixture of cadmium and tin metals or by reactive co-sputtering using twodifferent metal targets, that is, a cadmium target and a tin target. Thesputtering target(s) may be manufactured, formed, or shaped by anyprocess and in any shape, composition, or configuration suitable for usewith any appropriate sputtering tool, machine, apparatus, or system.

When depositing a substantially amorphous CTO layer 120 on the support110 by sputtering, the atomic concentration of cadmium and tin in thedeposited layer may be directly proportional to the atomic concentrationof cadmium and tin in the sputtering target(s). For particularprocesses, the atomic ratio of cadmium to tin in the sputteringtarget(s) is in a range from about 1.4:1 to about 3:1, and moreparticularly, in a range from about 1.5:1 to about 2.5:1, and still moreparticularly, in a range from about 1.7:1 to about 2.15:1. Forparticular processes, the atomic ratio of cadmium to tin in thesputtering target(s) is in a range from about 1.4:1 to about 2:1.

The thickness of the CTO layer 120 may be controlled by varying one ormore of the deposition process parameters. For example, the thickness ofthe CTO layer 120 may be engineered to be in a range of about 50-600 nm,and more particularly, in a range of about 100-500 nm, and still moreparticularly, in a range from about 200-400 nm.

Referring again to FIG. 1, the support 110 may be transparent over therange of wavelengths for which transmission through the support 110 isdesired. In one embodiment, the support 110 may be transparent tovisible light having a wavelength in a range of about 400-1000 nm. Thematerial for the support 110 may be selected such that the thermalexpansion coefficient of the support 110 is close to the thermalexpansion coefficient of the CTO layer 120 to prevent cracking orbuckling of the substantially amorphous CTO layer 120 during heattreatments. For particular configurations, other layers may be disposedbetween the CTO layer 120 and the support 110, such as, for example, areflective layer or a barrier layer 190, which is discussed below withreference to FIG. 2.

For certain configurations, the support 110 may comprise a materialcapable of withstanding heat treatment temperatures greater than about600° C., such as, for example silica and borosilicate glass. However,beneficially, the support 110 may comprise a material that has asoftening temperature lower than 600° C., such as, for example,soda-lime glass. Typically, it is not possible to use supports such assoda-lime glass for annealing of CTO because the annealing temperaturesemployed are greater than 600° C., which is greater than the softeningtemperature of soda-lime glass. Thus, use of supports such as soda limeglass is not feasible for fabrication of photovoltaic devices wheretemperatures greater than 600° C. are employed for annealing.Beneficially, the rapid thermal anneal used in the present manufacturingmethod (and described below) results in a rapid temperature increase ofthe support-CTO assembly and avoids continuous exposure of the supportto temperatures greater than 600° C. for an extended time period.Without being bound by any particular theory, it is believed that therapid thermal annealing step may heat the CTO layer much faster than thesupport due to the greater absorption of energy by the CTO layer.Accordingly, the rapid thermal anneal may allow the CTO layer to beheated to a temperature greater than the support, thus annealing the CTOlayer without softening the support. Thus, the present manufacturingmethod advantageously allows for use of low softening temperature (lessthan 600° C.) supports, such as, for example, soda-lime glass forforming a photovoltaic device.

Referring now to FIG. 9, the manufacturing method further includesplacing the support 110 with the CTO layer 120 within a chamber 12 of arapid thermal annealing system 10 and rapidly thermally annealing theCTO layer 120 by exposing the cadmium tin oxide layer 120 toelectromagnetic radiation to form the transparent oxide layer 120. Thetransparent oxide layer 120 disposed on the support 110 may form atransparent electrode 200. The rapid thermal anneal is performed withoutfirst pumping down the chamber 12. Thus, air is disposed within thechamber 12 during the rapid thermal anneal

Beneficially, because the rapid thermal anneal is performed in air,without first pumping down the chamber 12 and purging the chamber ofair, the time required to complete the rapid thermal anneal is reducedconsiderably, enabling the in-line performance of the rapid thermalanneal of the CTO layer 120 to form the transparent oxide layer (alsoindicated by reference numeral 120 herein). For example, the rapidthermal anneal of the CTO layer 120 may be performed in less thanfifteen minutes, and more particularly, in less than five minutes, andstill more particularly, in less than three minutes. Thus, forparticular processes, the rapid thermal anneal of the CTO layer 120 maybe performed in-line, such that the rapid thermal anneal is completedless than ten minutes after the deposition of the CTO layer (120) hasbeen completed.

In contrast, for the method disclosed in U.S. patent application Ser.No. 12/972,242, Joseph Darryl Michael et al., “Method for formingcadmium tin oxide layer and a photovoltaic device,” the rapid thermalanneal may be carried out under vacuum conditions, as explained inparagraph [0067] thereof. However, performing a rapid thermal annealunder vacuum conditions requires that the chamber be pumped and purged,which may be time consuming and require relatively expensive equipment.Although the time required to perform the rapid thermal anneal itselfmay be relatively quick (on the order of a few minutes), the timerequired to complete the entire anneal process (including pumping thechamber down and purging the chamber of air) is relatively long(typically over thirty minutes). Thus, rapid thermal annealing undervacuum is typically not suited for in-line annealing of the CTO layer120, as the overall process time is too long to satisfy the requirementsof in-line processing. Instead, the CTO-support assemblies would have tobe removed from the manufacturing line after the CTO (or other layers)is (are) deposited and annealed offline using the earlier rapid thermalanneal under vacuum technique. Beneficially, the present manufacturingmethod eliminates the need to first pump the chamber down, thusfacilitating performing the rapid thermal anneal inline, whilepermitting the use of less expensive equipment to perform the anneal.

The rapid thermal anneal may be performed using a variety of techniques.Generally, the terms “rapidly thermally annealing” and “rapid thermalannealing,” as used herein, refer to irradiating the CTO layer 120 at anincident power density in a range greater than about 200 Watts/cm² toform a substantially crystalline CTO layer 120. The term “incident powerdensity,” as used herein, refers to the power incident on the firstsurface 122 of the CTO layer 120 per unit surface area. For particularprocesses, rapid thermally annealing comprises irradiating a surface ofthe CTO layer 120 at an incident power density such that the heatingrate that the CTO layer is subjected to is greater than about 20°C./second, and more particularly, greater than about 100° C./second. Theterm “heating rate,” as used herein, refers to the average rate at whichthe CTO layer is heated, to reach the desired annealing temperature.Further, for particular processes, rapid thermally annealing comprisesirradiating a surface of the CTO layer 120 at an incident power densityand at a heating rate, such that the desired annealing temperature isreached in less than about 60 seconds.

The term “electromagnetic radiation,” as used herein, refers toradiation with electric and magnetic components. Electromagnetic (EM)radiation may be classified by wavelength into radio, microwave,infrared, visible region, ultraviolet (UV), X-rays and gamma rays. Forexample, infrared radiation is characterized by a wavelength greaterthan about 700 nm. For particular processes, rapid thermal annealing ofthe CTO layer 120 may comprise exposing the substantially amorphous CTOlayer 120 to high intensity EM radiation, such that controlled annealingof the CTO layer 120 is achieved. For example, rapid thermal annealingof the CTO layer 120 may comprise exposing the CTO layer 120 to highintensity infrared radiation, such that the CTO layer 120 absorbs asignificant portion of photons.

For particular processes, rapid thermal annealing of the CTO layer 120comprises exposing the CTO layer 120 to a high intensity EM radiationwith a defined intensity-wavelength spectrum, such that the CTO layer120 absorbs a significant portion of the incident light. As will beappreciated by those skilled in the art, the absorption profiles ofcrystalline CTO and amorphous CTO differ. Accordingly, the opticalproperties of amorphous (pre-anneal) and crystalline (post-anneal) CTOmay be advantageously used to achieve rapid thermal annealing in acontrolled manner.

As discussed in U.S. patent application Ser. No. 12/972,242, JosephDarryl Michael et al., “Method for forming cadmium tin oxide layer and aphotovoltaic device,” by heating the CTO layer with EM radiationcharacterized by wavelengths less than 300 nm may allow for more stableannealing of an amorphous CTO layer, as changes in optical properties ofthe CTO layer after annealing may not affect the power absorbed by thelayer. For particular processes, the CTO layer 120 may be annealed usingUV radiation characterized by wavelengths less than about 300 nm. Itshould be noted that the term “a wavelength in a range” refers to EMradiation having a spectrum of wavelengths in that range and is notlimited to a single wavelength or monochromatic radiation.

For particular processes, the CTO layer 120 may be annealed using EMradiation characterized by wavelengths less than about 600 nm. Asdiscussed in U.S. patent application Ser. No. 12/972,242, the absorptionprofile of crystalline CTO shows a significant reduction in absorptionbetween a wavelength range of about 350-600 nm. Accordingly, in suchinstances, the amount of power absorbed by the crystalline CTO layer islower than the power density absorbed by the substantially amorphous CTOlayer. Accordingly, in such embodiments, the heating rate of thesubstantially crystalline CTO layer may be lower than the substantiallyamorphous CTO layer, thus reducing the possibility of over-heating ofthe crystalline CTO layer.

For particular processes, the CTO layer 120 may be annealed using EMradiation characterized by wavelengths in a range of about 450-600 nm.As discussed in U.S. patent application Ser. No. 12/972,242, in thisrange, the rapid thermal annealing process may function essentially as a“self-limiting” process, that is, the act of crystallization preventsthe CTO layer from overheating. More generally, the selected wavelengthrange employed for rapid thermal annealing may depend in part on theoptical characteristics of the initial amorphous CTO layer, the opticalproperties of the resulting crystalline CTO layer, and the photonspectrum of the radiation source that is used.

As discussed in U.S. patent application Ser. No. 12/972,242, anincoherent light source may be employed to perform the rapid thermalanneal of the CTO layer 120. The term “light” as used herein refers toelectromagnetic radiation as defined above. The term “incoherent light”encompasses both light with different wavelengths, as well as light withthe same wavelength but that is out of phase. Further, the term“incoherent light source” encompasses both a single light source, aswell as multiple light sources. Example incoherent light sources includehalogen lamps, UV lamps, and high intensity discharge lamps. Examplelamps are indicated by reference numeral 14 in FIG. 9. It should benoted that the number and placement of the lamps 14 in FIG. 9 is purelyillustrative. For certain RTA systems, the lamps may be on one side, andfor others the lamps are disposed on different sides of the sample beingheated (as shown in FIG. 9, for example). The incoherent light sourcemay be configured to emit pulsed EM radiation, for example theincoherent light source may emit EM radiation at a fixed pulsed width,such that the duration of the exposure of the CTO layer to the EMradiation is characterized by the pulse width. An incoherent lightsource that emits EM radiation at a variable pulsed width may also beemployed. In addition to the pulse width, the incoherent light sourcemay be further characterized by the incident power density and the lamppower. Example incident power densities for the incoherent light sourcemay be in a range of about 100-500 watts/cm² and, more particularly, ina range of about 200-400 watts/cm². Example lamp powers for theincoherent light source may be in a range of about 1.4-2 kW and, moreparticularly, in a range from about 1.4-1.8 kW. The overall lamp powermay be provided by a single or multiple lamps, depending on the specificimplementation. Further, the lamps may have the same or differentpowers.

During the rapid thermal anneal, the CTO layer may be exposed to the EMradiation for about 1-180 seconds, and more particularly, for about5-120 seconds, and still more particularly, for about 10-90 seconds. Inaddition, the rapid thermal anneal may include multiple exposures of theCTO layer to the EM radiation. For example, the light source may bepulsed n times, wherein n is a range in a range from 2-20, and moreparticularly, may be pulsed 2-8 times. Depending on the specificimplementation, the pulse width may be the same for each thermalannealing step or may be varied for the different pulses. The number ofpulses and/or the pulse width may vary depending in part on thethickness of the support 110, the thickness of the CTO layer 120, and/orthe incident power density.

As discussed in U.S. patent application Ser. No. 12/972,242, the EMradiation is absorbed by the CTO layer 120 and converted into thermalenergy, resulting in a rapid increase in temperature of the layer, whichconcerts the substantially amorphous CTO to a substantially crystallineCTO. The percentage of this conversion may depend in part on the amountof incident power density absorbed by the substantially amorphous CTOlayer 120 and the thermal losses from the layer 120. Depending on thespecific process employed, the substantially amorphous CTO 120 layer mayabsorbs at least 10 percent of the incident power density, and moreparticularly, at least 50 percent of the incident power density, andstill more particularly, at least 80 percent of the incident powerdensity. As noted above, the amount of power density absorbed by thesubstantially amorphous CTO layer 120 may be advantageously controlledin part by tuning the energy wavelength spectra of the EM radiation.This, in turn, controls the heating rate and/or the treatmenttemperature. For particular processes, a substantially amorphous CTOlayer 120 is heated at a treatment temperature in a range of about700-1200° C., and more particularly, in a range of about 700-900° C.,and still more particularly, in a range of about 800-900° C. Treatmenttemperature as used herein refers to the temperature of the CTO layerafter being exposed to the EM radiation for a time duration sufficientto perform the anneal.

As noted above, rapid thermal annealing of the CTO layer 120 results inthe formation of a transparent layer 120. The resulting transparentlayer 120 may comprise a substantially uniform single-phasepolycrystalline CTO. For particular configurations, the substantiallycrystalline cadmium tin oxide may have an inverse spinel crystalstructure. Beneficially, the transparent layer may have the desiredelectrical and optical properties and may function as a transparentconductive oxide (TCO) layer. For certain configurations, the resultingtransparent layer 120 may further include an amorphous component, suchas for example, amorphous cadmium oxide, amorphous tin oxide, orcombinations thereof.

The transparent layer may be further characterized by its thickness,electrical properties, and/or optical properties. For particularconfigurations, the transparent layer 120 has a thickness in a range ofabout 100-600 nm, and more particularly, in a range of about 150-450 nm,and still more particularly, in a range of about 100-400 nm. Forparticular configurations, the transparent layer 120 has an averageelectrical resistivity (φ that is less than about 4×10⁻⁴ Ohm-cm, andmore particularly, less than about 2×10⁻⁴ Ohm-cm, and still moreparticularly, less than about 1.5×10⁻⁴ Ohm-cm. For example,resistivities (ρ) as low as about 1.4×10⁻⁴ Ohm-cm have been achieved forthe transparent oxide layer 120. For particular configurations, thetransparent layer 120 has an average optical transmission greater thanabout 80 percent and, more particularly, greater than about 95 percent.For particular configurations, the resulting transparent oxide layer 120has a sheet resistance R_(sh) less than about 7.5 Ohm/sq and, moreparticularly, the sheet resistance R_(sh) of the resulting transparentoxide layer 120 may be less than about 6.0 Ohm/sq.

Although the rapid thermal anneal is performed with air in the chamber12, the manufacturing method may further include flowing an inert gas orair (i.e., a continuous purging gas flow) through the chamber 12 duringthe rapid thermal anneal. For example, an inert gas, such as nitrogen orargon, or alternatively, additional air, may be flowed through thechamber during the rapid thermal anneal (RTA) in order to help collectany vapor escaping from the CTO during the RTA and to help direct thevapor towards a collector (not shown), such as a (relatively) coolsurface to capture the vapor. However, even for this specific process,it is not necessary to pump the chamber down prior to the RTA. Instead,the inert gas is simply used to help purge the chamber 12 of vaporsescaping from the CTO during the anneal, and the anneal is stillperformed with air in the chamber 12. However, when the chamber iscontinuously purged with an inert gas during the RTA, the oxygen levelin the chamber may be as low as about 100-500 parts per million (ppm)for larger PV modules.

In addition to the support 110/CTO 120 assembly shown in FIG. 1, therapid thermal anneal may be performed on a number of related structures,and the invention is not limited to a specific support/CTO assembly. Forexample, for the configuration shown in FIG. 3, the manufacturing methodfurther includes disposing a resistive, transparent buffer layer 170,for example a zinc tin oxide layer 170, on the CTO layer 120. Forparticular configurations, the zinc tin oxide comprises zinc stannate.Other suitable materials for the resistive, transparent buffer layer 170include, without limitation, include tin oxide, indium oxide (In₂O₃),zinc oxide, gallium oxide, aluminum oxide, ZnS:O, In(OH)₃,Mg_(1-x)Cd_(x)Te, MnSe, and Mn_(1-x)Zn_(x)Se (x=0.5-1), cadmium tinoxide, CdO—SnO₂, and mixtures thereof. Beneficially, the resistive,transparent buffer layer 170 may help to reduce the likelihood of havingweak diodes and/or shunts within the overall photovoltaic device.

For particular processes, the resistive, transparent buffer layer 170may be disposed on the CTO layer 120 prior to performing the rapidthermal anneal, such that the resistive, transparent buffer layer 170also undergoes the rapid thermal anneal. However, for other processes,the resistive, transparent buffer layer 170 may be disposed on the CTOlayer 120 after the rapid thermal anneal of the CTO layer, such that theheating of the resistive, transparent buffer layer 170 occurs, forexample, during the subsequent deposition of the absorber layer 130.

Similarly, for the configuration shown in FIG. 4, the manufacturingmethod further includes disposing a conductive layer 180 on the cadmiumtin oxide layer 120. For particular processes, the conductive layer 180may be disposed on the cadmium tin oxide layer 120 prior to performingthe rapid thermal anneal, such that the conductive layer 180 is oxidizedduring the RTA, becoming an optically transparent metal oxide layer 180.Example materials for the conductive layer 180 include, withoutlimitation, tin, aluminum, nickel, tantalum, titanium, indium, vanadium,zirconium, zinc, indium monoxide, tin monoxide, and titanium monoxide,and combinations or alloys thereof. Thus, after the RTA, a tin layer 180would comprise a tin oxide layer (also indicated by reference numeral180), for example. The other materials would similarly be oxidized,rendering them optically transparent. For particular configurations, theconductive layer comprises tin. For particular configurations, theconductive layer 180 is less than about 30 nm in thickness, and moreparticularly, has a thickness in a range of about 3-30 nm, and stillmore particularly has a thickness in a range of about 7-15 nm. In onenon-limiting example, a ten nanometer (10 nm) thick tin layer 180 wasdisposed on the CTO layer 120. However, the specific thickness selectedfor the conductive layer 180 will vary depending on the thickness of theCTO layer 120. Beneficially, the conductive layer 180 serves as a“getter” layer in that it prevents oxygen from penetrating into the CTOlayer 120.

Similarly, for the configurations shown in FIGS. 2 and 5, themanufacturing method further includes disposing a barrier layer 190 onthe support 110 prior to disposing the CTO layer 120, such that thebarrier layer 190 is disposed between the support 110 and the CTO layer120. Non-limiting example materials for the barrier layer includesilicon dioxide (SiO₂), trisilicon tetranitride (Si₃N₄), aluminum oxide(Al₂O₃), silicon oxynitride (SiO_(x)N_(y)), as well as multilayerstructures, such as SiO₂/Si₃N₄.

Similarly, for the configurations shown in FIGS. 5 and 6, themanufacturing method further includes disposing a conductive layer 180on the CTO layer 120. For particular processes, the conductive layer 180is disposed on the CTO layer 120 prior to performing the rapid thermalanneal (RTA), such that the conductive layer 180 becomes an opticallytransparent metal oxide layer 180. As noted above, suitable materialsfor the conductive layer include tin, aluminum, nickel, tantalum,titanium, indium, vanadium, zirconium, zinc, indium monoxide, tinmonoxide, and titanium monoxide, and combinations or alloys thereof. Forparticular configurations, a tin layer 180 with a thickness in a rangeof about 7-15 nm is disposed on the CTO layer 120 prior to performingthe RTA.

In addition, for the configurations shown in FIGS. 6 and 7, themanufacturing method further includes disposing a resistive, transparentbuffer layer 170 on the optically transparent metal oxide layer 180 (forexample, disposing a zinc tin oxide layer 170 on a tin oxide layer 180),in which case the heating of the transparent buffer layer 170 occursprimarily during the deposition of the absorber layer (discussed belowwith reference to FIG. 8). However, for other processes (alsoillustrated by FIGS. 6 and 7), the resistive, transparent buffer layer170 is disposed on the conductive layer 180 prior to performing the RTA,such that the resistive, transparent buffer layer 170 also undergoes theRTA.

For the configuration shown in FIG. 7, the manufacturing method furtherincludes disposing a semiconductor layer 185 on the resistive,transparent buffer layer 170. For example a CdS layer 185 may bedisposed on a zinc tin oxide layer 170. Depending on the particularprocess, the CdS 185 layer may be deposited before or after the rapidthermal anneal (RTA). For particular processes, the CdS 185 layer isdeposited after the RTA. Other suitable materials for semiconductorlayer 185 include indium (III) sulfide (In₂S₃), zinc sulfide (ZnS), zinctelluride (ZnTe), zinc selenide (ZnSe), cadmium selenide (CdSe),oxygenated cadmium sulfide (CdS:O), copper oxide (Cu₂O), amorphous ormicro-crystalline silicon and Zn(O,H) and combinations thereof.

A particular method of manufacturing a transparent oxide layer 120 foruse in a photovoltaic device 100 is described with reference to FIGS.1-9. As discussed above with reference to FIGS. 1 and 9, themanufacturing method includes disposing a cadmium tin oxide (CTO) layer120 on a support 110 and placing the support 110 with the cadmium tinoxide layer 120 within a chamber 12 of a rapid thermal annealing system10. Suitable compositions and deposition techniques for the CTO layer120 are provided above. The manufacturing method further includesrapidly thermally annealing the CTO layer 120 (for example, asubstantially amorphous CTO layer 120) by exposing the CTO layer 120 toelectromagnetic (EM) radiation to form the transparent oxide layer 120.Suitable techniques for performing the rapid thermal anneal are providedabove. Air is disposed within the chamber during the rapid thermalanneal at a concentration of at least one percent (1%) by volume.

Beneficially, by performing the rapid thermal anneal (RTA) in air, thereis no need to first pump the chamber 12 down prior to the RTA. Asdiscussed above, this considerably reduces the overall time needed toperform the RTA, thereby in-line rapid thermal annealing of the CTOlayer in a production setting, which increases throughput and reducescost (both unit cost and capital costs, as relatively expensive vacuumhandling systems can be avoided for the RTA system 10. As also noteabove, the manufacturing method may further include flowing an inert gasor air (i.e., a continuous purging gas flow) through the chamber 12during the rapid thermal anneal. For example, this may be performed tohelp collect any vapor escaping from the CTO during the RTA and to helpdirect the vapor towards a collector (not shown), such as a (relatively)cool surface to capture the vapor. However, even for this specificprocess, it is not necessary to pump the chamber down prior to the RTA.Instead, the inert gas is simply used to help purge the chamber 12 ofvapors escaping from the CTO during the anneal, and the anneal is stillperformed with air in the chamber 12. However, when the chamber iscontinuously purged with an inert gas during the RTA, the oxygen levelin the chamber may be as low as about 100-500 parts per million (ppm)for larger PV modules.

As described above with reference to FIGS. 2-7, a number of additionallayers may optionally be deposited to improve the function of the PVdevice 100. For example and as discussed above with reference to FIG. 3,the manufacturing method may further optionally include disposing aresistive, transparent buffer layer 170 on the cadmium tin oxide layer120. Example materials for the buffer layer include, without limitation,zinc tin oxide (for example, zinc stannate), tin oxide, indium oxide,zinc oxide, gallium oxide, aluminum oxide, ZnS:O, In(OH)₃,Mg_(1-x)Cd_(x)Te, MnSe, and Mn_(1-x)Zn_(x)Se (x=0.5-1), cadmium tinoxide, CdO—SnO₂, and combinations thereof. As noted above, theresistive, transparent buffer layer 170 may beneficially help to reducethe likelihood of having weak diodes and/or shunts within the overallphotovoltaic device. As also noted above, the resistive, transparentbuffer layer 170 may be disposed on the cadmium tin oxide layer 120prior to performing the rapid thermal anneal, such that the resistive,transparent buffer layer 170 also undergoes the rapid thermal anneal.For other processes, the resistive, transparent buffer layer 170 may bedisposed on the CTO layer 120 after the rapid thermal anneal of the CTOlayer, such that the heating of the resistive, transparent buffer layer170 may occur primarily during the subsequent deposition of the absorberlayer 130.

For particular processes, the rapid thermal anneal of the cadmium tinoxide layer 120 is performed is performed in-line, such that the rapidthermal anneal may be completed less than ten minutes after thedeposition of the cadmium tin oxide layer 120 has been completed. Thisability to perform the rapid thermal anneal in-line is particularlybeneficial. For example, the takt time for depositing the CTO layer 120may be approximately one minute, for particular manufacturing processes.So by achieving a comparable takt time for the rapid thermal anneal, thefootprint for the annealing chamber 12 may be roughly comparable to thefootprint for the CTO deposition system (not shown). In contrast, for arapid thermal annealing process performed under vacuum (namely, aprocess that required a pump and purge cycle), the total takt time forthe rapid thermal anneal may be at least 15-30 minutes, in which casethe footprint for the annealing chamber 12 would have to be about 15-30times the footprint for the CTO deposition system in order to performthe rapid thermal anneal under vacuum in-line with the CTO deposition.This would be prohibitively expensive, thereby necessitating theperformance of a RTA under vacuum off-line as a batch process in orderto control the overall capital cost for the manufacturing facility.

Referring now to FIG. 4, the manufacturing method may further optionallyinclude disposing a conductive layer 180 on the CTO layer 120 prior toperforming the rapid thermal anneal (RTA). Example materials for theconductive layer 180 include, without limitation, tin, aluminum, nickel,tantalum, titanium, indium, vanadium, zirconium, zinc, indium monoxide,tin monoxide, and titanium monoxide, and combinations or alloys thereof.For example a tin layer 180 with a thickness in a range of about 3-30 nmmay be deposited on the CTO layer 120 prior to the RTA. As noted above,the conductive layer 180 beneficially serves as a “getter” layer toprevent oxygen from penetrating the into the CTO layer 120. As alsonoted above, the conductive layer is oxidized during the RTA, such thatthe post-anneal layer 180 comprises an optically transparent oxide ofthe initially deposited metal. For example, after the RTA, a tin layer180 would comprise a tin oxide layer (also indicated by referencenumeral 180).

Referring now to FIGS. 2 and 5-7, the manufacturing method may furtheroptionally include disposing a barrier layer 190 on the support 110prior to disposing the CTO layer 120, such that the barrier layer 190 isdisposed between the support 110 and the CTO layer 120. Examplematerials for the barrier layer 190 are listed above. In addition, themanufacturing method may further optionally include disposing aconductive layer 180 on the CTO layer 120, as indicated in FIG. 5. Theconductive layer 180 may be deposited prior to performing the rapidthermal anneal, such that the conductive layer (180) becomes anoptically transparent metal oxide layer 180. Further, the manufacturingmethod may also optionally include disposing a resistive, transparentbuffer layer 170 (for example a zinc tin oxide layer 170) on theoptically transparent metal oxide layer 180, as shown for example inFIG. 6. For certain processes, the resistive, transparent buffer layer170 may be disposed on the conductive layer 180 prior to performing therapid thermal anneal, such that the resistive, transparent buffer layer170 also undergoes the rapid thermal anneal. However, for otherprocesses, the resistive, transparent buffer layer 170 may be disposedon the optically transparent metal oxide layer 180 after performing therapid thermal anneal, such that the resistive, transparent buffer layer170 may not be heated until the subsequent deposition of the absorberlayer 130 (as discussed below with reference to FIG. 8). In addition,and as indicated for example in FIG. 7, the manufacturing method mayalso optionally include disposing a semiconductor layer 185 on theresistive, transparent buffer layer 170. For example a CdS layer 185 maybe disposed on a zinc tin oxide layer 170 before or after the RTA,depending on the particular process. Other suitable materials for thesemiconductor layer 185 are provided above.

In addition, the manufacturing method for the photovoltaic device 100will typically further include disposing an absorber layer 130 on thesemiconductor layer 185, as indicated, for example, in FIG. 8. Theabsorber layer may comprise a material selected from the groupconsisting of cadmium telluride, cadmium zinc telluride, cadmium sulfurtelluride, cadmium manganese telluride, cadmium magnesium telluride andcombinations thereof. As noted above, the semiconductor layer 185 maycomprise a material selected from the group consisting of cadmiumsulfide (CdS), indium (III) sulfide (In₂S₃), zinc sulfide (ZnS), zinctelluride (ZnTe), zinc selenide (ZnSe), cadmium selenide (CdSe),oxygenated cadmium sulfide (CdS:O), copper oxide (Cu₂O), amorphous ormicro-crystalline silicon and Zn(O,H) and combinations thereof. Thesematerials should also be understood to include the alloys thereof. Forexample, CdTe can be alloyed with zinc, magnesium, manganese, and/orsulfur to form cadmium zinc telluride, cadmium copper telluride, cadmiummanganese telluride, cadmium magnesium telluride and combinationsthereof. It bears noting that the above-mentioned photo-activesemiconductor materials may be used alone or in combination. Further,these materials may be present in more than one layer, each layer havingdifferent type of photo-active material or having combinations of thematerials in separate layers.

For particular configurations, the absorber layer 130 comprises a p-typematerial, for example p-type CdTe, and has a thickness less than aboutthree (3) μm and, more particularly, has a thickness less than about two(2) μm, and less than about 1.5 μm for certain configurations. Thematerials listed above may be actively doped to be p-type. Suitabledopants vary based on the semiconductor material. For CdTe, suitablep-type dopants include, without limitation, copper, gold, nitrogen,phosphorus, antimony, arsenic, silver, bismuth, and sodium.

Further, the manufacturing method for the photovoltaic device 100 willtypically also include disposing a second electrically conductive layer140 on the absorber layer 130, as indicated in FIG. 8, for example.Although not expressly shown, the manufacturing method for the PV device100 may further optionally include disposing one or more layers betweenthe absorber layer 130 and the second electrically conductive layer 140.For example, a p+ layer (not shown) could be disposed between theabsorber 130 and the back contact 140 (FIG. 8) to reduce the electricalresistance between the absorber and the back contact. Example materialsfor the second electrically conductive layer 140 include, withoutlimitation gold, platinum, molybdenum, aluminum, chromium, nickel, andsilver. In addition, for certain configurations, another metal layer(not shown), for example, aluminum, may be disposed on the secondelectrically conductive layer 140 to provide lateral conduction to theoutside circuit. For the arrangement shown in FIG. 8, the secondelectrically conductive layer 140 serves as the back contact for thesuperstrate-based PV device 100.

Example 1

A 300 nm thick layer of CTO was deposited by reactive sputtering ofCd/Sn target in a 100% oxygen environment on a borosilicate glasssubstrate. The resulting assembly was then subjected to a rapid thermalanneal (RTA) in standard ambient air conditions using a square quartzholder (not shown) using a RTA system sold under the tradename AS-One100, which is commercially available from ANNEALSYS. The maximum powerfor this RTA system is 30 KW. The maximum sample size this RTA systemcan accommodate is 100 mm. The RTA was performed at a lamp power of 85%(which corresponds to about 25.5 kW for this 30 kW system, and which isequivalent to 325 W/cm²) for 55 seconds and resulted in a transparentlayer with a sheet resistance R_(sh) of 5.7 Ohms/sq, an averageelectrical resistivity (ρ) of 1.71×10⁻⁴ Ohm-cm, and a weightedabsorption of 3.84%.

Example 2

A 20 nm thick Si₃N₄/SiO₂ barrier later was deposited by RF sputtering ona borosilicate glass substrate. A 300 nm thick layer of CTO wasdeposited by RF sputtering of a ceramic CTO target on the barrier layer.A 15 nm thick layer of tin was deposited on the CTO by DC sputtering.The resulting assembly was then subjected to a rapid thermal anneal(RTA) in standard ambient air conditions using a square quartz holder(not shown) using the AS-One 100 RTA system from ANNEALSYS. The RTA wasperformed at a lamp power of 85% (which is equivalent to 325 W/cm²) for27 seconds and resulted in a transparent layer with a sheet resistanceR_(sh) of 5.985 Ohms/sq, an average electrical resistivity (ρ) of1.80×10⁻⁴ Ohm-cm, and a weighted absorption of 4.71%.

Example 3

A 20 nm thick Si₃N₄/SiO₂ barrier later was deposited by RF sputtering ona borosilicate glass substrate. A 300 nm thick layer of CTO wasdeposited by RF sputtering of ceramic CTO target on the barrier layer. A15 nm thick layer of tin was deposited on the CTO by DC sputtering. Theresulting assembly was then subjected to a rapid thermal anneal (RTA) instandard ambient air conditions using a graphite susceptor (not shown)using the AS-One 100 RTA system from ANNEALSYS. The RTA was performedusing two pulses, the first pulse at a lamp power of 30% (equivalent to115 W/cm²) for 60 seconds, and the second pulse at a lamp power of 20%for 30 seconds and resulted in a transparent layer with a sheetresistance R_(sh) of 4.687 Ohms/sq, an average electrical resistivity(ρ) of 1.41×10⁻⁴ Ohm-cm, and a weighted absorption of 5.16%.

Example 4

A 20 nm thick Si₃N₄/SiO₂ barrier later was deposited by RF sputtering ona borosilicate glass substrate. A 300 nm thick layer of CTO wasdeposited by RF sputtering of a ceramic CTO target on the barrier layer.The resulting assembly was then subjected to a rapid thermal anneal(RTA) in standard ambient air conditions using a graphite susceptor (notshown) using the AS-One 100 RTA system from ANNEALSYS. The RTA wasperformed using two pulses, the first pulse at a lamp power of 30%(equivalent to 115 W/cm²) for 60 seconds, and the second pulse at a lamppower of 20% for 30 seconds and resulted in a transparent layer with asheet resistance R_(sh) of 7.2 Ohms/sq, an average electricalresistivity (ρ) of 2.16×10⁻⁴ Ohm-cm, and a weighted absorption of 4.83%.

Beneficially, because the rapid thermal anneal is performed in air,without first pumping down the chamber and purging the chamber of air,the time required to complete the rapid thermal anneal is reducedconsiderably, enabling the in-line performance of the rapid thermalanneal of the CTO layer to form the transparent oxide layer. Inaddition, the reduced processing time reduces the footprint for thisprocessing step and may reduce the equipment cost as well.

Although only certain features of the invention have been illustratedand described herein, many modifications and changes will occur to thoseskilled in the art. It is, therefore, to be understood that the appendedclaims are intended to cover all such modifications and changes as fallwithin the true spirit of the invention.

1. A method of manufacturing a transparent oxide layer, themanufacturing method comprising: disposing a cadmium tin oxide layer ona support; placing the support with the cadmium tin oxide layer within achamber of a rapid thermal annealing system; and rapidly thermallyannealing the cadmium tin oxide layer by exposing the cadmium tin oxidelayer to electromagnetic radiation to form the transparent oxide layer,wherein the rapid thermal anneal is performed without first pumping downthe chamber.
 2. The manufacturing method of claim 1, wherein air isdisposed within the chamber during the rapid thermal anneal.
 3. Themanufacturing method of claim 1, further comprising flowing an inert gasor air through the chamber during the rapid thermal anneal.
 4. Themanufacturing method of claim 1, further comprising disposing aresistive, transparent buffer layer on the cadmium tin oxide layer. 5.The manufacturing method of claim 4, wherein the resistive, transparentbuffer layer comprises a material selected from the group consisting ofzinc tin oxide, zinc stannate, tin oxide, indium oxide, zinc oxide,gallium oxide, aluminum oxide, cadmium tin oxide, CdO—SnO₂ andcombinations thereof and is disposed on the cadmium tin oxide layerprior to performing the rapid thermal anneal, such that the resistive,transparent buffer layer also undergoes the rapid thermal anneal.
 6. Themanufacturing method of claim 1, wherein the rapid thermal anneal of thecadmium tin oxide layer is performed in less than fifteen minutes. 7.The manufacturing method of claim 6, wherein the rapid thermal anneal ofthe cadmium tin oxide layer is performed in less than three minutes. 8.The manufacturing method of claim 1, wherein the rapid thermal anneal ofthe cadmium tin oxide layer is performed in-line, such that the rapidthermal anneal is completed less than ten minutes after the depositionof the cadmium tin oxide layer has been completed.
 9. The manufacturingmethod of claim 1, wherein the transparent oxide layer has a sheetresistance R_(sh) less than about 7.5 Ohm/sq.
 10. The manufacturingmethod of claim 1, wherein the transparent oxide layer has an electricalresistivity (ρ) less than about 2×10⁻⁴ Ohm-cm.
 11. The manufacturingmethod of claim 10, wherein the transparent oxide layer has anelectrical resistivity (ρ) less than about 1.5×10⁻⁴ Ohm-cm.
 12. Themanufacturing method of claim 1, further comprising disposing aconductive layer on the cadmium tin oxide layer.
 13. The manufacturingmethod of claim 12, wherein the conductive layer is disposed on thecadmium tin oxide layer prior to performing the rapid thermal anneal,such that the conductive layer becomes an optically transparent metaloxide layer.
 14. The manufacturing method of claim 12, wherein theconductive layer comprises a material selected from the group consistingof tin, aluminum, nickel, tantalum, titanium, indium, vanadium,zirconium, zinc, indium monoxide, tin monoxide, and titanium monoxide,and combinations or alloys thereof.
 15. The manufacturing method ofclaim 14, wherein the conductive layer is less than about thirtynanometers (30 nm) in thickness.
 16. The manufacturing method of claim1, further comprising disposing a barrier layer on the support prior todisposing the cadmium tin oxide layer, such that the barrier layer isdisposed between the support and the cadmium tin oxide layer.
 17. Themanufacturing method of claim 16, further comprising disposing aconductive layer on the cadmium tin oxide layer.
 18. The manufacturingmethod of claim 17, wherein the conductive layer is disposed on thecadmium tin oxide layer prior to performing the rapid thermal anneal,such that the conductive layer becomes an optically transparent metaloxide layer, the manufacturing method further comprising disposing aresistive, transparent buffer layer on the optically transparent metaloxide layer.
 19. The manufacturing method of claim 18, furthercomprising disposing a semiconductor layer on the resistive, transparentbuffer layer.
 20. A method of manufacturing a transparent oxide layer,the manufacturing method comprising: disposing a cadmium tin oxide layeron a support; placing the support with the cadmium tin oxide layerwithin a chamber of a rapid thermal annealing system; and rapidlythermally annealing the cadmium tin oxide layer by exposing the cadmiumtin oxide layer to electromagnetic radiation to form the transparentoxide layer, wherein air is disposed within the chamber during the rapidthermal anneal at a concentration of at least one percent (1%) byvolume.
 21. The manufacturing method of claim 20, further comprisingflowing an inert gas or air through the chamber during the rapid thermalanneal.
 22. The manufacturing method of claim 20, further comprisingdisposing a resistive, transparent buffer layer on the cadmium tin oxidelayer.
 23. The manufacturing method of claim 22, wherein the resistive,transparent buffer layer is disposed on the cadmium tin oxide layerprior to performing the rapid thermal anneal, such that the resistive,transparent buffer layer also undergoes the rapid thermal anneal. 24.The manufacturing method of claim 20, wherein the rapid thermal annealof the cadmium tin oxide layer is performed is performed in-line, suchthat the rapid thermal anneal is completed less than ten minutes afterthe deposition of the cadmium tin oxide layer has been completed. 25.The manufacturing method of claim 20, further comprising disposing aconductive layer on the cadmium tin oxide layer prior to performing therapid thermal anneal, such that the conductive layer becomes anoptically transparent metal oxide layer, wherein the conductive layercomprises a material selected from the group consisting of tin,aluminum, nickel, tantalum, titanium, indium, vanadium, zirconium, zinc,indium monoxide, tin monoxide, and titanium monoxide, and combinationsor alloys thereof, and wherein the conductive layer has a thickness in arange of about 3-30 nm.
 26. The manufacturing method of claim 20,further comprising disposing a barrier layer on the support prior todisposing the cadmium tin oxide layer, such that the barrier layer isdisposed between the support and the cadmium tin oxide layer.
 27. Themanufacturing method of claim 26, further comprising disposing aconductive layer on the cadmium tin oxide layer prior to performing therapid thermal anneal, such that the conductive layer becomes anoptically transparent metal oxide layer, wherein the conductive layercomprises a material selected from the group consisting of tin,aluminum, nickel, tantalum, titanium, indium, vanadium, zirconium, zinc,indium monoxide, tin monoxide, and titanium monoxide, and combinationsor alloys thereof.
 28. The manufacturing method of claim 27, furthercomprising disposing a resistive, transparent buffer layer on theconductive layer prior to performing the rapid thermal anneal, such thatthe resistive, transparent buffer layer also undergoes the rapid thermalanneal.
 29. The manufacturing method of claim 27, further comprisingdisposing a resistive, transparent buffer layer on the opticallytransparent metal oxide layer.
 30. The manufacturing method of claim 29,further comprising disposing a semiconductor layer on the resistive,transparent buffer layer.